报告人：Seung-Tak Ryu

时 间：2022/10/24 下午15:00

主持人：唐希源 助理教授

Abstract:   

Since late 2000’s, SAR ADCs have become one of the most popular ADC architectures showing not only excellent energy efficiency but also competitive conversion speed owing to the digital-friendly compact structure and architectural evolution in deep submicron technologies. Being utilized as sub building blocks, SAR ADCs could also enhance the performance of other types of ADCs such as pipelined, delta-sigma, and even flash ADCs. This talk discusses how SAR ADCs could have improved the ADC performance with various architectural modifications.

Biography:  

SEUNG-TAK RYU received the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004, respectively.

From 2001 to 2002, he was with the University of California, San Diego, CA, USA, as a Visiting Researcher, sponsored through the Brain Korea 21 (BK21) Program. In 2004, he joined Samsung Electronics, Yongin, South Korea, where he was involved in mixed-signal IP development. From 2007 to 2009, he was with the Information and Communications University (ICU), Daejeon, as an Assistant Professor. He has been with the School of Electrical Engineering, KAIST, since 2009, where he is currently a Professor. His research interests include analog and mixed-signal IC design with an emphasis on data converters and sensors.

He is a member of TPCs of Asian Solid-State Circuits Conference (A-SSCC), the Custom Integrated Circuits Conference (CICC), and European Solid-State Circuits Conference (ESSCIRC). He has served on the Technical Program Committee (TPC) for the IEEE International Solid-State Circuits Conference (ISSCC) and also served as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) twice. He is an Associate Editor of the IEEE SOLID-STATE CIRCUITS LETTERS (SSCL) since 2018 and a Distinguished Lecturer for the IEEE Solid-State Circuits Society (2021-2022).